1. Field of the Invention
The present invention relates to a method of forming multi-level interconnects for connecting a plurality of semiconductor devices. More particularly, the present invention relates to a method of forming a dual damascene structure.
2. Description of the Related Art
As the level of circuit integration increased, dimensions of each semiconductor device are reduced and the number of metallic interconnects needed for linking up devices increases correspondingly. However, as size of devices is reduced and the number of interconnects is increased, high product yield and reliability of metallic interconnects is difficult to achieve. Consequently, the semiconductor industry is now striving towards the production of interconnects with good conductivity and operating characteristics despite having a smaller contact area.
In the backend process for fabricating semiconductor devices, line width of metallic lines is also reduced. Therefore, current density sustainable by the metallic lines must be increased correspondingly. High-density current flowing along a conventional aluminum wire often results in electromigration. Electromigration can cause serious reliability problems in the semiconductor device.
To avoid electromigration in deep submicron devices, metallic material less vulnerable to electromigration such as copper has been used. Due to the low resistivity, low electromigration and easy deposition of copper, copper is now widely used for fabricating multi-level interconnects.
Since copper is resistant to most gaseous etchants, copper interconnects are not manufactured by conventional means. In general, the copper interconnects are formed by a dual damascene process. The dual damascene process includes the step of etching out a via opening for enclosing the metallic interconnect in a dielectric layer, and then filling the via opening with metal. This process is capable of producing high-quality copper interconnects with a relatively high yield.
FIGS. 1A through 1C are schematic, cross-sectional views showing the steps for producing a conventional dual damascene structure. As shown in FIG. 1A, a substrate 100 having a conductive layer 102 therein is provided. A dielectric layer 104 is formed on the substrate 100 and the conductive layer 102. Photolithographic and etching processes are conducted to form a via opening 105a and a trench 105b in the dielectric layer 104 to expose a portion of the conductive layer 102. A conformal barrier layer 106 is formed over the substrate 100, and then a copper layer 108 that fills the via opening 105a and the trench 105b is formed over the dielectric layer 104. A planarization step is performed to remove the barrier layer 106 and the copper layer 108 above the dielectric layer 104. The planarization step can be, for example, chemical-mechanical polishing.
Copper atoms can diffuse rapidly in silicon oxide and can easily react with silicon to produce copper-silicon alloy. Since the copper-silicon alloy can result in device malfunction or unwanted bridging between neighboring metallic interconnects, the barrier layer 106 is needed to prevent the diffusion of copper atoms from the copper layer 108 to the dielectric layer 104.
As shown in FIG. 1B, a silicon nitride layer 110 and an inter-metal dielectric (IMD) layer 112 are sequentially formed over the dielectric layer 104 and the copper layer 108. Since silicon nitride is a compact material, the silicon nitride layer 110 is also capable of preventing the diffusion of copper atoms into the IMD layer 112.
As shown in FIG. 1C, a patterned photoresist layer (not shown) is formed over the IMD layer 112. Using the silicon nitride layer 110 as an etching stop layer, the IMD layer 112 is etched to form a via opening 114 that exposes a portion of the silicon nitride layer 110. Due to the presence of the silicon nitride layer 110 between the dielectric layer 104 and the IMD layer 112, over-etching of the IMD layer 112 into the dielectric layer 104 can be prevented. A second etching step is carried out to remove the silicon nitride layer 110 at the bottom of the via opening 114 so that a portion of the copper layer 108 is exposed.
The via opening 114 is typically formed by reactive ion etching. However, during the etching step, energetic particles in the plasma may also bombard the copper layer 108. Consequently, some copper ions 116 are sputtered out and later deposited back onto the sidewalls of the via opening 114 or the reacting station, leading to copper contamination.
In addition, oxygen plasma is also used to remove any residual photoresist material after the via opening 114 is formed. Since oxygen may react with copper in the copper layer 108 to produce copper oxide, a layer of loose copper oxide, which can have a thickness of about 1600 angstroms, forms over the exposed portion of the copper layer 108. When a barrier layer is subsequently formed over the copper layer, conductivity of metallic interconnect may drop and via resistance may increase.
In general, a cleaning step is also conducted after the via opening 114 is formed so that polymers deposited on the sidewalls of the opening 114 can be removed. However, most organic cleaning agents contain water, which that may lead to copper corrosion and oxidation. Moreover, the polymer on the sidewalls of via opening is removed by immersing the wafer in a chemical bath filled with cleaning solution. The amount of copper ions in the cleaning solution is hard to control. Therefore, under some circumstances, the copper ions in the cleaning solution may be re-deposited back onto the wafer, causing unwanted contamination.